//
// Created by 32827 on 2024/7/13.
//

#ifndef STM32F407RTOS_YZL_SPI_ADS1220_H
#define STM32F407RTOS_YZL_SPI_ADS1220_H
#include "yzl_driver.h"
#include "yzl_softport.h"
#define YZL_ADS1220_RESET 0b00000110
#define YZL_ADS1220_START_SYNC 0b00001000
#define YZL_ADS1220_POWER_DOWN 0b00000010
#define YZL_ADS1220_RDATA 0b00010000
#define YZL_ADS1220_RREG(start,size) 0b0010##start##size
#define YZL_ADS1220_WREG(start,size) 0b0100##start##size

#define YZL_ADS1220_CFG0_ADD 00
#define YZL_ADS1220_CFG1_ADD 01
#define YZL_ADS1220_CFG2_ADD 10
#define YZL_ADS1220_CFG3_ADD 11

typedef struct YZL_ADS1220_CFG{
    uint8_t cfg0;
    uint8_t cfg1;
    uint8_t cfg2;
    uint8_t cfg3;
} YZL_ADS1220_CFG_DEF;

#define YZL_ADS1220_CFG0_MUX_Pos 4
#define YZL_ADS1220_CFG0_MUX_Msk (0xFUL << YZL_ADS1220_CFG0_MUX_Pos)
#define YZL_ADS1220_CFG0_GAIN_Pos 1
#define YZL_ADS1220_CFG0_GAIN_Msk (0x7UL << YZL_ADS1220_CFG0_GAIN_Pos)
#define YZL_ADS1220_CFG0_PGA_BYPASS_Pos 0
#define YZL_ADS1220_CFG0_PGA_BYPASS_Msk (0x1UL << YZL_ADS1220_CFG0_PGA_BYPASS_Pos)

#define YZL_ADS1220_CFG1_DR_Pos 5
#define YZL_ADS1220_CFG1_DR_Msk (0x7UL << YZL_ADS1220_CFG1_DR_Pos)
#define YZL_ADS1220_CFG1_MODE_Pos 3
#define YZL_ADS1220_CFG1_MODE_Msk (0x3UL << YZL_ADS1220_CFG1_MODE_Pos)
#define YZL_ADS1220_CFG1_CM_Pos 2
#define YZL_ADS1220_CFG1_CM_Msk (0x1UL << YZL_ADS1220_CFG1_CM_Pos)
#define YZL_ADS1220_CFG1_TS_Pos 1
#define YZL_ADS1220_CFG1_TS_Msk (0x1UL << YZL_ADS1220_CFG1_TS_Pos)
#define YZL_ADS1220_CFG1_BCS_Pos 0
#define YZL_ADS1220_CFG1_BCS_Msk (0x1UL << YZL_ADS1220_CFG1_BCS_Pos)

#define YZL_ADS1220_CFG2_VREF_Pos 6
#define YZL_ADS1220_CFG2_VREF_Msk (0x3UL << YZL_ADS1220_CFG2_VREF_Pos)
#define YZL_ADS1220_CFG2_50_60_Pos 4
#define YZL_ADS1220_CFG2_50_60_Msk (0x3UL << YZL_ADS1220_CFG2_50_60_Pos)
#define YZL_ADS1220_CFG2_PSW_Pos 3
#define YZL_ADS1220_CFG2_PSW_Msk (0x1UL << YZL_ADS1220_CFG2_PSW_Pos)
#define YZL_ADS1220_CFG2_IDAC_Pos 0
#define YZL_ADS1220_CFG2_IDAC_Msk (0x7UL << YZL_ADS1220_CFG2_IDAC_Pos)

#define YZL_ADS1220_CFG3_I1MUX_Pos 5
#define YZL_ADS1220_CFG3_I1MUX_Msk (0x7UL << YZL_ADS1220_CFG3_I1MUX_Pos)
#define YZL_ADS1220_CFG3_I2MUX_Pos 2
#define YZL_ADS1220_CFG3_I2MUX_Msk (0x7UL << YZL_ADS1220_CFG3_I2MUX_Pos)
#define YZL_ADS1220_CFG3_DRDYM_Pos 1
#define YZL_ADS1220_CFG3_DRDYM_Msk (0x1UL << YZL_ADS1220_CFG3_DRDYM_Pos)
#define YZL_ADS1220_CFG3_RESERVED_Pos 0
#define YZL_ADS1220_CFG3_RESERVED_Msk (0x1UL << YZL_ADS1220_CFG3_RESERVED_Pos)

YZF_RESULT yzl_ads1220_init(YZL_ADS1220_CFG_DEF *cfg,YZF_SPI_POINTER spi,YZL_GPIO cs3);
uint32_t yzl_ads1220_read(YZF_SPI_POINTER spi,YZL_GPIO rdy,YZL_GPIO cs3);
YZF_RESULT yzl_ads1220_sleep(YZF_SPI_POINTER spi,YZL_GPIO cs3);
YZF_RESULT yzl_ads1220_wake(YZF_SPI_POINTER spi,YZL_GPIO cs3);
#endif //STM32F407RTOS_YZL_SPI_ADS1220_H
